RTL/ASIC Design Engineer

RTL/ASIC Design Engineer

San Jose, CA (100% Onsite)

12 + Months

$75-78/HR

Must-Haves:

5-6+ years ASIC/RTL design experience

Proven tape-outs on production silicon

SOC RTL block design & IP integration

Lint, CDC, RDC experience

Synthesis & static timing analysis

Responsibilities:

Write micro-architecture docs; own block design & implementation (timing, area, power)

Partner with arch, verification, and physical design teams through tape-out

Support silicon bring-up and cross-functional problem solving

Implement design automation

Experience Required (5-6+ yrs):

ASIC RTL design and SoC IP integration

Synthesis, static timing analysis, and optimizations

Nice to Have:

Timing constraints, scripting (Python/Perl/Tcl), low-power design, ARM/AXI/CHI protocols, interconnect design

Education:

Bachelor’s degree required

Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.

Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals. To learn more, please visit .

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.