Packaging Design Engineer

Title: Packaging Design Engineer

Overview:

We are seeking an experienced Packaging Design Engineer to develop innovative, reliable, and cost-effective IC packaging solutions. The ideal candidate will have hands-on expertise in advanced substrate design, interconnect optimization, and high-speed signal integrity.

Responsibilities:

• Create and maintain netlists and BGA designs based on project inputs.
• Conduct feasibility studies to determine optimal pad layouts, interconnect structures, and substrate parameters for various IC devices and applications.
• Define substrate stack-ups, routing strategies, and via structures to meet electrical and mechanical requirements.
• Design substrates for RF, digital, high-speed, and mixed-signal die applications.
• Ensure SI/PI compliance when routing high-speed interfaces such as DDR and SERDES.
• Apply expertise in UCIE (Advanced and Standard) and HBM technologies.
• Develop and implement design rule checks (DRC) to ensure compliance with manufacturing, assembly, and design guidelines.
• Optimize die breakout patterns for signal and high-power performance.
• Work with HDI substrate technologies, materials, and layout rules for maximum performance and reliability.
• Validate designs against electrical, thermal, mechanical, and manufacturability standards.
• Support wire bond, flip-chip, and advanced packaging (2.5D, 3D, RDL, embedded passives, etc.) designs.
• Contribute to CoWoS (Chip-on-Wafer-on-Substrate) interposer design and substrate optimization.
• Collaborate with OSATs, applying knowledge of their design rules and capabilities.

Qualifications:

• Bachelor’s degree in Electrical or Electronics Engineering.
• 4–8+ years of experience in IC package design and development.
• Strong proficiency with Cadence Allegro Package Designer.
• Solid understanding of SI/PI principles, HDI substrate technologies, and advanced packaging architectures.